The present invention relates to a converter, such as an analog to digital convener, wherein the converter has plurality of input channels, and the sequence in which those channels are converted is programmable.
Multi channel analog to digital converters typically have a single converts therein wvith two or more channels multiplexed into the single convertor through transmission gates. Typically one of the plurality of available channels is selected by explicitly writing the channel number into the control register of the converter using a suitable interface, such as a serial interface.
Such an arrangement is, in terms of processor overhead, cumbersome and inefficient as the channel register has to be programed each the user wants to change the channel to be converted. That is to say, converting P distinct channels requires P distinct control register write operations.
To overcome these problems, some multi channel analog to digital converters have been provided with some form of automatic cycling.
A converter commercially available from Texas Instruments as a xe2x80x98TLV2548xe2x80x99 is an 8 channel converter which has a programmable auto channel sweep function. The user programmes a control register therein, and two of the bits in the control register are decoded to offer one of four preset channel sequences. No other channel sequences are available. The channel sequences are set out as follows:
Thus, the user must choose one of the preset sequences and cannot mask out channel at their own choosing.
According to a first aspect of the present invention, there is provided an analog to digital converter, where the converter has N input channels, and where any one or more of the N input channels can be converted in order in response to a control word, the unselected channels being skipped.
It is thus possible to provide an analog to digital converter in which the sequence cycle time to convert all of the channels in a user definable sequence is substantially proportional to the number of channels selected, and wherein the user can freely define those channels which are to be converted in sequence. The user""s definition of which channels are to be converted can be supplied as a single command.
Advantageously the analog to digital converter is operable in other modes of operation, such that the number of the next channel to be converted can be explicitly written into the control register, and/or automatic cycling through each and every channel can be instructed.
Advantageously each conversion result output from the converter includes a channel identifier in order to explicitly identify the number of the channel that has been concerted a digital representation of the analog input at that channel. Preferably the output of the converter is provided as a serial word, thereby minimising the number of output pins required by the converter.
Advantageously the control word indicating which channels are to be converted is held in a control register. The register is advantageously N bits long such that each bit corresponds to an associated one of the channels. Thus, control of the converter can be simplified. The control register may be one of a plurality of registers provided for controlling the operation of the digital to analog converter,
According to a second aspect of the present invention there is provided a circuit comprising a plurality of latches having respective inputs and outputs, wherein the latches are arranged such that the output of a latch is provided to the input of a subsequent latch and the latches are responsive to a latch signal, and wherein in a first mode of operation a latch selected by a respective latch mode control signal is arranged to latch a signal received at its input in response to a latch signal, and in a second mode of operation selected by the latch mode control sign the input at the latch is transferred directly to its output irrespective of the state of the latch signal.
The term xe2x80x9clatchxe2x80x9d as used herein refers to the generic sense of operation where a device has an input, an output and a control line, and where following a trigger event the output is held steady irrespective of changes occurring at the input.
The xe2x80x9clatchingxe2x80x9d function can be implemented by combinational logic functions such as a D type flip-flop or a D type latch. From a review of textbooks it appears that some authors regard the terms as being synonymous. However, some workers in the art ascribe precise and different meanings to the terms. In particular a latch is regarded as a level triggered device whereas a flip-flop is sometimes regarded as an edge triggered device.
In order to avoid confusion, a device that provides a generic latching function will be referred to herein as a xe2x80x9clatchxe2x80x9d. If a specific need to describe the device as being level triggered is identified, then the device will be described as being a level triggered latch. Where the edge triggering nature of a device is important, then it will be described as being edge triggered, for example an edge triggered flip-flop.
Also, in general, a latch (when not used in the generic sense) describes a device that when not in the latched mode propagates the signals at its input directly to its output.
According to a third aspect of the invention, there is provided a counter circuit comprising a plurality of latches arranged in a chain, each latch arranged to operate in a first mode of operation where, in response to a mode control signal, a latch is arranged to latch a data signal received at a first input of the latch and in a second mode of operation where, in response to the mode control sign the latch is arranged to pass said data signal directly to the input of a subsequent latch in the chain.
It is thus possible to provide a counter circuit having a plurality of elements arranged to shift a single logic xe2x80x9conexe2x80x9d from one element to a succeeding element in response to a clock signal, and wherein each element is further responsive to a select signal for selecting the element such that, if the element is selected, it participates in the shifting of the signal, and if not selected the element merely propagates the signal.
Such a counter circuit is preferably associated with a control register such that the mode control signal for the or each element in the circuit is held by the register. Advantageously an output gate is also controlled in response to the mode control signal such hat internal transient signals propagating through the circuit are not propagated from outputs of unselected ones of the elements. Thus the mode control signal acts to select whether a latch and associated gate will participate in the formation of a shift or ring counter; or whether the latch will effectively function as a wire and the gate will be held at a predetermined output.
Preferably each element comprises at least one latch, for example a D (delay) type latch and means for inhibiting the latching operation of the latch. A first inhibiting means may be provided by effectively removing the latch from the chain of elements when it is not selected and bypassing it with a suitable logic gate or combination of gates.
In a preferred arrangement, each element in the latch comprises first and second D type level triggered latches arranged in series, the D input of the first latch is arranged to receive data from a preceding element, or from a injection node in the case of the first element in the chain. The output of the level triggered D type latch is provided to the D input of the second level triggered D type latch, and the output of the second latch is then provided as an input to a subsequent element. Level triggered D type latches have the property that the input signal occurring at the data input is immediately propagated (subject to internal gate propagation delays) to the output thereof whilst the xe2x80x98clockxe2x80x99 signal at a clock input is in a first logic state, and the data is latched when the clock is at a second logic state. Advantageously a master clock is provided from a clock line to the clock input of the first level triggered D type latch via a suitable gate, such as an AND or NAND gate, such that transitions on the clock line only occur if an element select signal supplied to one of the inputs of the gates is selected, and such that, if the gate is not selected the D type latch is arranged such that it is held in a mode where the signal at the data input is propagated directly to the output thereof. Similarly, the second D type latch has its clock signal provided through a gating arrangement such that, if the particular element is not selected it is also arranged such that data always propagates directly from its D input to its output.